What is the course about?

This Espresso course is designed for VLSI beginners and covers the basics of timing and timing analysis in a quick and consistent way. The course has 10 Units and each unit is based on the practical concepts required to understand the digital circuit timing. The course serves as a foundation course for engineers, who wish to pursue their career in the area of VLSI design!

The duration of this course is only 45 minutes and it contains video sessions with subtitles for easy understanding of the concepts. The content is presented in such a way that, it explains basics to complex scenarios in a very simple way!

To gain and to apply the concepts, assignment and quizzes are also included.

What our customers say about the course...

Great STA course for Beginners

,,Nice course for beginner who want to understand the static Timing Analysis. All concepts are explained in very simple way ?. I like the course ? . Waiting for Advance STA course."

Neeraj Bani, Senior engineer, (2021)

These course modules are really helpful to start with VLSI

,,This course covered Basics of Timing, Basics of STA, Timing paths, Skew, Slack, Timing issues and Maximum frequency calculation. For a beginner's point of view, these course modules are really helpful to start with VLSI. These modules taught, help in company written tests and even in Interviews. This course is done in white board which helps in connecting and understanding the topics easily."

Nithin Kamath K, Manipal Institute of Technology, Student, (2021)

Satisfactory

,,I have already studied this in my academics, so this was a good revision for me. It is definitely a good course for beginners. If I was a beginner I would have expected more detailed explanation with some solved examples when it came to set up slack and hold slack concepts as they might be very confusing to beginners. Overall this is satisfactory in my opinion."

Meghana, (2021)

Course content

Course instructors

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Prof Vaibbhav Taraate

Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 21 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, SystemVerilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog and SystemVerilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.