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Vaibbhav Taraate

RTL Design using Verilog

RTL Design With Practical Scenarios

  • PRO
  • mandatory workload 14 h 17 min
  • language English
  • topics Computer Science
  • purchase available 79
  • free certificate included Certificate included

What is the course about?

The course "RTL Design Using Verilog" is a 14 hours course and useful to VLSI Beginners. The course covers the basics of complex RTL design using Verilog and is useful as a foundation course to RTL designers. The main course highlights are:

  1. Video sessions on Verilog constructs and their role in RTL design.
  2. Videos on RTL design strategies and performance improvement
  3. Videos on the Finite State Machine RTL design strategies.
  4. Videos on the RTL design strategies for complex designs
  5. Exercises and Assignments

If you wish to pursue a career in the VLSI domain then the course can be used as foundation course! The course covers the RTL design concepts with the practical scenarios.

Course Structure

The course has 11 chapters and covers the Verilog constructs and their role in the RTL design!

  1. Introduction to Design Flow and HDL

  2. Concurrency and continuous Assignments

  3. Procedural always block and Combinational Design

  4. RTL Design for Combinational Logic and Guidelines

  5. Verification and Testbenches

  6. Sequential Design using Verilog Constructs

  7. Other important constructs useful during design and verification

  8. RTL design Guidelines

  9. Finite State Machines

  10. Performance Improvement at RTL Level

  11. Complex designs and Strategies while coding the RTL

What is included in this course

By enrolling in this course, you will gain access to:

• All Course Material

• Challenging Assignments and EDA tool-based sessions

• Exercises and Quizzes

• Flexible Time Management


Upon completion of this course, you will receive:

• A Certificate of Participation

 

In addition, this course offers flexible time management. With a workload of 12 hours, the suggested course length is about 4-5 weeks. If you can't spare 3-4 hours a week or would rather finish the course faster, you can do so as well. Take as little or as much time as you need and complete the course at your own pace.

Course content

Chapter 1
Introduction to Design Flow and HDL
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Introduction
8 min
Preview
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Basic Design Flow
13 min
Preview
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RTL Design to Implementation
10 min
Preview
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Introduction to Hardware Description
15 min
Preview
Chapter 2
Concurrency and continuous Assignments
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Concept of Concurrency
8 min
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Module Instantiation
10 min
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ISE Video Tutorial
10 min
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RTL Design Using Xilinx Vivado
10 min
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Functional Simulation Using Xilinx Vivado
12 min
Chapter 3
Procedural always block and Combinational Design
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Important Verilog Constructs
5 min
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Procedural always block
10 min
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Functional Simulation of 2:1 MUX
8 min
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Incomplete Sensitivity List
12 min
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The always @ *
12 min
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Assignments
30 min
Chapter 4
RTL Design for Combinational Logic and Guidelines
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Bitwise operator and buses in RTL design
10 min
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Sequential Construct 'if else'
10 min
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Nested 'if else' construct
12 min
Preview
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RTL design for combinational logic
45 min
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The case construct
6 min
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Unintentional Latches
8 min
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Verilog Parameter and role during design
5 min
Chapter 5
Verification and Testbenches
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Applications and Use of Verilog Constructs
30 min
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Force Level Simulation
10 min
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Use of 'initial' block
6 min
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Testbench for combinational design
10 min
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Verilog stratified event queue
10 min
Chapter 6
Sequential Design using Verilog Constructs
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Let us recall Digital Design Fundamentals!
10 min
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Blocking Assignments
10 min
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Non Blocking Assignments (NBA)
10 min
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Basics of Sequential Design
15 min
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Intentional Latches
10 min
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Use of Reset in the Design
5 min
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Assignments on Sequential Design
45 min
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RTL design of Ring COunter
60 min
Chapter 7
Other important constructs useful during design a…
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The casex and casez in Verilog
8 min
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The function and task in Verilog
10 min
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Use of begin-end versus fork-join
10 min
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The inter and intra delay assignments
10 min
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The display tasks used during simulation
10 min
Chapter 8
RTL design Guidelines
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Grouping the Terms
5 min
Preview
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Reordering of the blocking assignments and synthesis
6 min
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Reordering of Non Blocking Assignments
6 min
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Assignment to find and fix potential issues in the RTL
45 min
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Area Optimization at RTL level
60 min
Chapter 9
Finite State Machines
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Introduction to FSM
10 min
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Let us understand the state diagrams
10 min
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Moore Machine : RTL Design Strategy
8 min
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Mealy Machine: RTL Design Strategy
5 min
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Sequence detector RTL design
45 min
Chapter 10
Performance Improvement at RTL Level
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Area Optimization Using RTL Ttweaks
10 min
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Concept of Maximum Frequency for Design
5 min
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Assignment on Speed Improvement
9 min
Chapter 11
Complex designs and Strategies while coding the R…
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How we can code RTL for complex designs?
10 min
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Strategies for the complex designs
10 min
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Architecture and RTL design for 8-bit ALU
45 min
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Multiple clock domain and Level Synchronizes
15 min
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Concluding Session
5 min

What will you learn?

You will be able to learn the RTL design using Verilog and synthesizable and non-synthesizable constructs. The course will also cover a few advanced techniques like optimization, performance improvements, FSM design strategies and the strategies for the complex design!

What is the target audience?

As a participant, it is recommended that you have a basic understanding of the digital design techniques

If you are an Electronics, Electrical, Instrumentation or Computer Science engineer then you can opt for this course! Also, if you are only interested in the field of VLSI, ASIC, FPGA then you can join this course too and learn the design using Verilog and use the synthesizable and non-synthesizable constructs!

Course instructors

  • PRO
  • mandatory workload 14 h 17 min
  • language English
  • topics Computer Science
  • purchase available 79
  • free certificate included Certificate included
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Individuals

Course access including certificate

Get access to the content of the course and verify your course participation and learnings with an official document.

79 €*
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