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Vaibbhav Taraate

RTL Design using Verilog

  • PRO
  • 14 h 17 min
  • English
  • Computer Science
  • 79
  • Certificate included

What is the course about?

The course "RTL Design Using Verilog" is a 14 hours course and useful to VLSI Beginners. The course covers the basics of complex RTL design using Verilog and is useful as a foundation course to RTL designers. The main course highlights are:

  1. Video sessions on Verilog constructs and their role in RTL design.
  2. Videos on RTL design strategies and performance improvement
  3. Videos on the Finite State Machine RTL design strategies.
  4. Videos on the RTL design strategies for complex designs
  5. Exercises and Assignments

If you wish to pursue a career in the VLSI domain then the course can be used as foundation course! The course covers the RTL design concepts with the practical scenarios.

Course Structure

The course has 11 chapters and covers the Verilog constructs and their role in the RTL design!

  1. Introduction to Design Flow and HDL

  2. Concurrency and continuous Assignments

  3. Procedural always block and Combinational Design

  4. RTL Design for Combinational Logic and Guidelines

  5. Verification and Testbenches

  6. Sequential Design using Verilog Constructs

  7. Other important constructs useful during design and verification

  8. RTL design Guidelines

  9. Finite State Machines

  10. Performance Improvement at RTL Level

  11. Complex designs and Strategies while coding the RTL

What is included in this course

By enrolling in this course, you will gain access to:

• All Course Material

• Challenging Assignments and EDA tool-based sessions

• Exercises and Quizzes

• Flexible Time Management

Upon completion of this course, you will receive:

• A Certificate of Participation


In addition, this course offers flexible time management. With a workload of 12 hours, the suggested course length is about 4-5 weeks. If you can't spare 3-4 hours a week or would rather finish the course faster, you can do so as well. Take as little or as much time as you need and complete the course at your own pace.

Course content

Chapter 1
Introduction to Design Flow and HDL
Basic Design Flow
RTL Design to Implementation
Introduction to Hardware Description
Chapter 2
Concurrency and continuous Assignments
Concept of Concurrency
Module Instantiation
ISE Video Tutorial
RTL Design Using Xilinx Vivado
Functional Simulation Using Xilinx Vivado
Chapter 3
Procedural always block and Combinational Design
Important Verilog Constructs
Procedural always block
Functional Simulation of 2:1 MUX
Incomplete Sensitivity List
The always @ *
Chapter 4
RTL Design for Combinational Logic and Guidelines
Bitwise operator and buses in RTL design
Sequential Construct 'if else'
Nested 'if else' construct
RTL design for combinational logic
The case construct
Unintentional Latches
Verilog Parameter and role during design
Chapter 5
Verification and Testbenches
Applications and Use of Verilog Constructs
Force Level Simulation
Use of 'initial' block
Testbench for combinational design
Verilog stratified event queue
Chapter 6
Sequential Design using Verilog Constructs
Let us recall Digital Design Fundamentals!
Blocking Assignments
Non Blocking Assignments (NBA)
Basics of Sequential Design
Intentional Latches
Use of Reset in the Design
Assignments on Sequential Design
RTL design of Ring COunter
Chapter 7
Other important constructs useful during design a…
The casex and casez in Verilog
The function and task in Verilog
Use of begin-end versus fork-join
The inter and intra delay assignments
The display tasks used during simulation
Chapter 8
RTL design Guidelines
Grouping the Terms
Reordering of the blocking assignments and synthesis
Reordering of Non Blocking Assignments
Assignment to find and fix potential issues in the RTL
Area Optimization at RTL level
Chapter 9
Finite State Machines
Introduction to FSM
Let us understand the state diagrams
Moore Machine : RTL Design Strategy
Mealy Machine: RTL Design Strategy
Sequence detector RTL design
Chapter 10
Performance Improvement at RTL Level
Area Optimization Using RTL Ttweaks
Concept of Maximum Frequency for Design
Assignment on Speed Improvement
Chapter 11
Complex designs and Strategies while coding the R…
How we can code RTL for complex designs?
Strategies for the complex designs
Architecture and RTL design for 8-bit ALU
Multiple clock domain and Level Synchronizes
Concluding Session

What will you learn?

You will be able to learn the RTL design using Verilog and synthesizable and non-synthesizable constructs. The course will also cover a few advanced techniques like optimization, performance improvements, FSM design strategies and the strategies for the complex design!

What is the target audience?

As a participant, it is recommended that you have a basic understanding of the digital design techniques

If you are an Electronics, Electrical, Instrumentation or Computer Science engineer then you can opt for this course! Also, if you are only interested in the field of VLSI, ASIC, FPGA then you can join this course too and learn the design using Verilog and use the synthesizable and non-synthesizable constructs!

Course instructors


Course access including certificate

Get access to the content of the course and verify your course participation and learnings with an official document.

79 €*

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