What is the course about?
The course "RTL Design Using Verilog" is a 14 hours course and useful to VLSI Beginners. The course covers the basics of complex RTL design using Verilog and is useful as a foundation course to RTL designers. The main course highlights are:
- Video sessions on Verilog constructs and their role in RTL design.
- Videos on RTL design strategies and performance improvement
- Videos on the Finite State Machine RTL design strategies.
- Videos on the RTL design strategies for complex designs
- Exercises and Assignments
If you wish to pursue a career in the VLSI domain then the course can be used as foundation course! The course covers the RTL design concepts with the practical scenarios.
Course Structure
The course has 11 chapters and covers the Verilog constructs and their role in the RTL design!
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Introduction to Design Flow and HDL
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Concurrency and continuous Assignments
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Procedural always block and Combinational Design
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RTL Design for Combinational Logic and Guidelines
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Verification and Testbenches
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Sequential Design using Verilog Constructs
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Other important constructs useful during design and verification
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RTL design Guidelines
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Finite State Machines
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Performance Improvement at RTL Level
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Complex designs and Strategies while coding the RTL
What is included in this course
By enrolling in this course, you will gain access to:
• All Course Material
• Challenging Assignments and EDA tool-based sessions
• Exercises and Quizzes
• Flexible Time Management
Upon completion of this course, you will receive:
• A Certificate of Participation
In addition, this course offers flexible time management. With a workload of 12 hours, the suggested course length is about 4-5 weeks. If you can't spare 3-4 hours a week or would rather finish the course faster, you can do so as well. Take as little or as much time as you need and complete the course at your own pace.
Course content
Chapter
1
Introduction to Design Flow and HDL
Chapter
2
Concurrency and continuous Assignments
Chapter
3
Procedural always block and Combinational Design
Chapter
4
RTL Design for Combinational Logic and Guidelines
Chapter
5
Verification and Testbenches
Chapter
6
Sequential Design using Verilog Constructs
Chapter
7
Other important constructs useful during design a…
Chapter
8
RTL design Guidelines
Chapter
9
Finite State Machines
Chapter
10
Performance Improvement at RTL Level
Chapter
11
Complex designs and Strategies while coding the R…
What will you learn?
You will be able to learn the RTL design using Verilog and synthesizable and non-synthesizable constructs. The course will also cover a few advanced techniques like optimization, performance improvements, FSM design strategies and the strategies for the complex design!
What is the target audience?
As a participant, it is recommended that you have a basic understanding of the digital design techniques
If you are an Electronics, Electrical, Instrumentation or Computer Science engineer then you can opt for this course! Also, if you are only interested in the field of VLSI, ASIC, FPGA then you can join this course too and learn the design using Verilog and use the synthesizable and non-synthesizable constructs!
Course instructors
Individuals
Course access including certificateGet access to the content of the course and verify your course participation and learnings with an official document.
Organisations & Groups
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(price varies depending on access amount)
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