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Prof Vaibbhav Taraate

RTL Design using Verilog

  • PRO
  • 14h 17 min
  • English
  • 79

À propos du cours

The course "RTL Design Using Verilog" is a 14 hours course and useful to VLSI Beginners. The course covers the basics of complex RTL design using Verilog and is useful as a foundation course to RTL designers. The main course highlights are:

  1. Video sessions on Verilog constructs and their role in RTL design.
  2. Videos on RTL design strategies and performance improvement
  3. Videos on the Finite State Machine RTL design strategies.
  4. Videos on the RTL design strategies for complex designs
  5. Exercises and Assignments

If you wish to pursue a career in the VLSI domain then the course can be used as foundation course! The course covers the RTL design concepts with the practical scenarios.

What will I learn?

You will be able to learn the RTL design using Verilog and synthesizable and non-synthesizable constructs. The course will also cover a few advanced techniques like optimization, performance improvements, FSM design strategies and the strategies for the complex design!

Who should take this course

As a participant, it is recommended that you have a basic understanding of the digital design techniques

If you are an Electronics, Electrical, Instrumentation or Computer Science engineer then you can opt for this course! Also, if you are only interested in the field of VLSI, ASIC, FPGA then you can join this course too and learn the design using Verilog and use the synthesizable and non-synthesizable constructs!

Course Structure

The course has 11 chapters and covers the Verilog constructs and their role in the RTL design!

  1. Introduction to Design Flow and HDL

  2. Concurrency and continuous Assignments

  3. Procedural always block and Combinational Design

  4. RTL Design for Combinational Logic and Guidelines

  5. Verification and Testbenches

  6. Sequential Design using Verilog Constructs

  7. Other important constructs useful during design and verification

  8. RTL design Guidelines

  9. Finite State Machines

  10. Performance Improvement at RTL Level

  11. Complex designs and Strategies while coding the RTL

What is included in this course

By enrolling in this course, you will gain access to:

• All Course Material

• Challenging Assignments and EDA tool-based sessions

• Exercises and Quizzes

• Flexible Time Management


Upon completion of this course, you will receive:

• A Certificate of Participation

 

In addition, this course offers flexible time management. With a workload of 12 hours, the suggested course length is about 4-5 weeks. If you can't spare 3-4 hours a week or would rather finish the course faster, you can do so as well. Take as little or as much time as you need and complete the course at your own pace.

Inscrivez-vous ou contactez-nous !

Nous proposons des cours de formation continue en ligne professionnels à des particuliers comme à des organisations.

Particuliers

Certificat de participation

Vérifie ta participation active au cours par un document officiel

79 €*

Organisations

Si ce cours vous intéresse en tant qu’organisation, et que vous souhaitez acheter un accès de cours pour plusieurs employés, nous vous informons sur les avantages d’achats en grande quantité.

Nous établissons une offre pour vous et votre équipe.

*Nos prix contiennent la TVA.

Vous avez des questions ?

Pour les questions sur les contenus des cours, veuillez vous adresser à support@iversity.org.
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