Vaibbhav Taraate

FSM Design using Verilog

  • PRO
  • 7h 26 min
  • English
  • Computer Science
  • 79
  • Certificate included

What is the course about?

The course "FSM Design using Verilog" is almost  8 hours course and useful to RTL design engineers. The course covers the RTL design strategies for FSM designs and complex FSM design techniques. The course is useful as a foundation course and can be best tool to design FSM controllers using Verilog. The main course highlights are:

  1. Video sessions with practical design concepts and Verilog constructs
  2. Videos on RTL design for FSM and Performance improvement
  3. Videos on the data and control path synthesis
  4. Videos on the complex FSM designs and FSM controller design using Verilog
  5. Exercises, QUIZZES and Assignments

If you wish to pursue a career in the RTL Design domain then the course can be used as foundation course! In the RTL design, the designer should know about the various kinds of FSMs and RTL design strategies for complex designs. The course covers the FSM design techniques, RTL design using Verilog for the FSM controllers which are helpful to the RTL design engineers!

Course Structure

The course has 10 chapters and covers the RTL design techniques and strategies for FSM designs and performance improvement!

  1. Let us revise Verilog Synthesizable and non-synthesizable constructs

  2. RTL design using Verilog

  3. Finite State Machines

  4. Moore machines

  5. Mealy machines

  6. Moore Sequence detectors

  7. Mealy Sequence detectors

  8. FSM Performance Improvement Techniques

  9. FSM data and control path synthesis

  10. Concluding Session 

What is included in this course

By enrolling in this course, you will gain access to:

•The Course Videos

• Challenging Assignments

• Exercises and Quizzes

• Flexible Time Management

Upon completion of this course, you will receive:

• A Certificate of Participation

In addition, this course offers flexible time management. With a workload of 8 hours, the suggested course length is about 3-4 weeks. If you can’t spare 2-3 hours a week or would rather finish the course faster, you can do so as well. Take as little or as much time as you need and complete the course at your own pace.

Course content

Chapter 1
Let us revise Verilog Synthesizable and non-synth…
Welcome to the course
About the course
Verilog Synthesizable Constructs
The always procedural block
The synthesizable constructs if....else and case...endcase
Sequential design using Verilog
Verilog non-synthesizable constructs
Testbench as a driver
Chapter 2
RTL design using Verilog
State register using Verilog
Next state and output logic using Verilog
Chapter 3
Finite State Machines
Basics of FSM
Basics of State Diagram
Chapter 4
Moore FSM
Let us design the RTL for FSM
Moore FSM and design using Verilog
Tool Based Session on RTL design of Moore FSM
Assignment on the sequential circuit design
Chapter 5
Mealy FSM
Mealy Machine and design using Verilog
Tool Based Session on RTL design of Mealy FSM
Assignment on the Mealy machine design
Chapter 6
Moore Sequence Detector
Let us design the RTL for sequence detector!
Moore Sequence detector
RTL Design : Moore sequence detector
Assignment on the Moore sequence detector
Chapter 7
Mealy Sequence Detector
Design planning for the Mealy sequence detector
RTL Design : Mealy Sequence Detector
Assignment on the Mealy sequence detector
Chapter 8
FSM Performance Improvement Techniques
FSM performance improvement techniques
Tool based session on optimization of FSM
Tool based session on the speed improvement of FSM
Chapter 9
FSM Data and Control Path Synthesis
FSM Controller Design
Design to understand about the data and control path
Assignment on the data and control path synthesis
Chapter 10
Concluding session
What next?
Course concluding session

What will you learn?

You will be able to learn the basics of RTL design for FSM controllers and design techniques. The course will also cover a few advanced techniques like FSM controller designs and the data and control path synthesis for FSM controllers with performance improvement!

What is the target audience?

As a participant, it is recommended that you have a basic understanding of the digital design techniques and Verilog .

If you are an Electronics, Electrical, Instrumentation or Computer Science engineer then you can opt for this course! Also, if you are only interested in the field of VLSI, ASIC, FPGA then you can join this course too and learn the basics of RTL design using Verilog for FSM!

Course instructors


Course access including certificate

Get access to the content of the course and verify your course participation and learnings with an official document.

79 €*

Organisations & Groups

If you are interested in purchasing several course accesses for your employees or a group of people, click the button below.

(price varies depending on access amount)

* Our prices include VAT

Have a question?

We are ready to help you!

Support Kite illustration

Have a question?

We are ready to help you!

Corporate clients please use our B2B contact form

For questions regarding the course contents please contact our customer support