What is the course about?
The course "FSM Design using Verilog" is almost 8 hours course and useful to RTL design engineers. The course covers the RTL design strategies for FSM designs and complex FSM design techniques. The course is useful as a foundation course and can be best tool to design FSM controllers using Verilog. The main course highlights are:
- Video sessions with practical design concepts and Verilog constructs
- Videos on RTL design for FSM and Performance improvement
- Videos on the data and control path synthesis
- Videos on the complex FSM designs and FSM controller design using Verilog
- Exercises, QUIZZES and Assignments
If you wish to pursue a career in the RTL Design domain then the course can be used as foundation course! In the RTL design, the designer should know about the various kinds of FSMs and RTL design strategies for complex designs. The course covers the FSM design techniques, RTL design using Verilog for the FSM controllers which are helpful to the RTL design engineers!
What will I learn?
You will be able to learn the basics of RTL design for FSM controllers and design techniques. The course will also cover a few advanced techniques like FSM controller designs and the data and control path synthesis for FSM controllers with performance improvement!
Who should take this course
As a participant, it is recommended that you have a basic understanding of the digital design techniques and Verilog .
If you are an Electronics, Electrical, Instrumentation or Computer Science engineer then you can opt for this course! Also, if you are only interested in the field of VLSI, ASIC, FPGA then you can join this course too and learn the basics of RTL design using Verilog for FSM!
The course has 10 chapters and covers the RTL design techniques and strategies for FSM designs and performance improvement!
Let us revise Verilog Synthesizable and non-synthesizable constructs
RTL design using Verilog
Finite State Machines
Moore Sequence detectors
Mealy Sequence detectors
FSM Performance Improvement Techniques
FSM data and control path synthesis
- Concluding Session
What is included in this course
By enrolling in this course, you will gain access to:
•The Course Videos
• Challenging Assignments
• Exercises and Quizzes
• Flexible Time Management
Upon completion of this course, you will receive:
• A Certificate of Participation
In addition, this course offers flexible time management. With a workload of 8 hours, the suggested course length is about 3-4 weeks. If you can’t spare 2-3 hours a week or would rather finish the course faster, you can do so as well. Take as little or as much time as you need and complete the course at your own pace.
Prof Vaibbhav Taraate
Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, SystemVerilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog and SystemVerilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.
EinzelpersonenKurszugang inklusive Zertifikat
Beinhaltet den Zugang zum Kurs und ein Teilnahmezertifikat als Download.