What is the course about?
The course " Performance Improvement Techniques for Design" is a short duration course. The course discusses the various performance improvement techniques for ASIC and FPGA based designs. If you wish to pursue your career in the VLSI domain then the course is useful to understand the area, speed and power optimization and improvement techniques!
The practical scenarios are also highlighted with the PowerPoint presentations and videos with subtitles. Although it is a short duration course the course includes two assignments and 4 quizzes! The course covers the following important topics
1. Practical scenarios and design case study
2. Optimization strategies
3. Performance improvement for design
4. Complex designs and strategies
5. Important practical scenarios
6. Role of EDA tools
Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 21 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, SystemVerilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog and SystemVerilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.
IndividualsCourse access including certificate
Get access to the content of the course and verify your course participation and learnings with an official document.