About this course

The course " Digital Design in VLSI Perspective" is a 12 hours course and useful to VLSI Beginners. The course covers the basics to complex Digital Design techniques and is useful as a foundation course to beginners. The main course highlights are:

1. Video sessions with practical design concepts
2. Videos on performance improvement
3. Videos on the Finite State Machines
4. Videos on the complex design techniques
5. Exercises and Assignments

If you wish to pursue a career in the VLSI domain then the course can be used as foundation course! In the system design, the designer should know about the various kinds of elements and their role. The course covers the digital design techniques which are helpful to the VLSI beginners!

What will I learn?

You will be able to learn the basics of digital design and design techniques. The course will also cover a few advanced techniques like optimization and FSM designs!

Who should take this course

As a participant, it is recommended that you have a basic understanding of the digital circuits.

If you are an Electronics, Electrical, Instrumentation or Computer Science engineer then you can opt for this course! Also, if you are only interested in the field of VLSI, ASIC, FPGA then you can join this course too and learn the basics of digital design and design techniques!

Course Structure

The course has 11 chapters and covers the basics of digital design elements and their role in the system design!

1. Introduction

2. Arithmetic Logic Resources

3. Let Us Apply Fundamentals

4. Code Converters and Design

5. Multiplexer as Universal Logic

6. Decoders, Encoders and Priority Logic

7. Area Optimization for Combinational Design

8. Basics of Sequential Design

9. Counters and Shift Registers and Design Approach

10. Sequential Circuit Delays and Timing Analysis

11. Finite State Machines

What is included in this course

By enrolling in this course, you will gain access to:

• All Course Material

• Challenging Assignments

• Exercises and Quizzes

• Flexible Time Management



Upon completion of this course, you will receive:

• A Certificate of Participation

In addition, this course offers flexible time management. With a workload of 12 hours, the suggested course length is about 4-5 weeks. If you can’t spare 3-4 hours a week or would rather finish the course faster, you can do so as well. Take as little or as much time as you need and complete the course at your own pace.

Course instructors

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Prof Vaibbhav Taraate

Vaibbhav Taraate is Entrepreneur and Mentor at “1 Rupee S T”. He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur, in 1995 and secured a gold medal for standing first in all engineering branches. He has completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog, SystemVerilog and VHDL. He has worked with few multinational corporations as consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog and SystemVerilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high-speed VLSI designs, and architecture design of complex SOCs.